The present invention is generally directed to charge pumps for use in phase-locked loops (PLLs) and delay locked loops (DLLs), and more specifically, to an integrated circuit that uses a dynamic charge balance circuit to control the charge current in a charge pump.
In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits (ICs), such as application specific integrated circuit (ASIC) chips, radio frequency integrated circuits (RFIC), central processing unit (CPU) chips, digital signal processor (DSP) chips and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, microprocessor, high-speed data transceiver, and the like).
In many integrated circuits, the clock signals that drive an integrated circuit are generated by a frequency synthesizer phase-locked loop (PLL) or a delay locked loop (DLL). PLLs and DLLs are well known to those skilled in the art and have been extensively written about. The dynamic performance of the frequency synthesizer that is used to generated clock signals is dependent on several parameters, including the natural frequency (Fn) , the damping factor (DF), the crossover frequency (F0) and the ratio of the comparison frequency (Fc) to the crossover frequency. The first three parameters depend on the voltage controlled oscillator (VCO) gain (K0), the F/B (N) divider value, the charge pump current (Ic), and the loop filter components. The last parameter (i.e., the ratio of comparison frequency to crossover frequency) is dependent on the input divider (M) value, as well as the frequency of the input clock itself.
The performance of the frequency synthesizer is also dependent on the performance of the charge pump located in the PLL or DLL. The charge pump pulse timing jitter and pulse amplitude noise both contribute to synthesizer phase noise. A typical charge pump includes circuitry to avoid what is known as the xe2x80x9cdead zone.xe2x80x9d The dead zone occurs at or near the PLL xe2x80x9clockxe2x80x9d state when the phase error is very small and the loop gain would otherwise approach zero. To avoid this problem, both the Pump Up current source and the Pump Down current source of a charge pump are turned ON simultaneously for a brief period at the end of each phase detector cycle. However, to reduce charge pump output noise, it is desirable to reduce the ON time of the charge pump output in the xe2x80x9clockxe2x80x9d state.
As the simultaneous ON time is reduced, the goal is to balance the injected charge from the Pump Up current source and the Pump Down current source so that a periodic glitch caused by charge imbalance is not injected into the loop filter, thereby causing frequency spurs on the VCO output. This is difficult to do because the transistor devices used in the Pump Up and Pump Down current sources are different channel type devices with different parasitic characteristics. The problem is further exacerbated when the ON time is reduced to lower the phase noise contribution of the charge pump.
Therefore, there is a need in the art for improved frequency synthesizers for use in generating reference frequency signals. In particular, there is a need in the art for improved charge pumps for use in phase-locked loops or delay-locked loops. More particularly, there is a need for charge pumps that minimize the charge current imbalances in lock state.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an improved charge pump. According to an advantageous embodiment of the present invention, the charge pump comprises: 1) a first current mirror capable of injecting a first charging current, I(U), onto a loop filter coupled to an output of the charge pump and injecting a second charging current, I(U)/M, onto an integrator capacitor, wherein the first and second charging currents are controlled by a first common control signal such that the first charging current mirrors the second charging current by a factor M; and 2) a second current mirror capable of draining a first discharging current, I(D), from the loop filter and draining a second discharging current, I(D)/M, from the integrator capacitor, wherein the first and second discharging currents are controlled by a second common control signal such that the first discharging current mirrors the second discharging current by the factor M. The charge pump further comprises: 3) a sampling circuit capable of coupling the second charging current and the second discharging current to the integrator capacitor so that the integrator capacitor is one of: i) charged and ii) discharged by a difference current between the second charging current and the second discharging current; and 4) a control circuit capable of detecting a voltage difference between a voltage on the loop filter and a voltage on the integrator capacitor, wherein the control circuit is operable to adjust the first common control signal to minimize the voltage difference.
According to one embodiment of the present invention, the first current mirror comprises: 1) a first charging current source capable of injecting the first charging current onto the loop filter; and 2) a second charging current source capable of injecting the second charging current onto the integrator capacitor.
According to another embodiment of the present invention, the second current mirror comprises: 1) a first discharging current source capable of draining the first discharging current from the loop filter; and 2) a second discharging current source capable of draining the second discharging current from the integrator capacitor.
According to still another embodiment of the present invention, the control circuit comprises an amplifier having a non-inverting input coupled to the integrator capacitor and an inverting input coupled to the loop filter.
According to yet another embodiment of the present invention, the first common control voltage is generated on an output of the amplifier.
According to a further embodiment of the present invention, the control circuit, in response to an increase in voltage on the integrator capacitor, adjusts the first common control voltage so that the second charging current is reduced.
According to a still further embodiment of the present invention, the adjustment of the first common control voltage by the control circuit also reduces the first charging current.
According to a yet further embodiment of the present invention, the control circuit, in response to a decrease in voltage on the integrator capacitor, adjusts the first common control voltage so that the second charging current is increased.
In one embodiment of the present invention, the adjustment of the first common control voltage by the control circuit also increases the first charging current.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.